`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:47:40 10/23/2013 
// Design Name: 
// Module Name:    BaudRateGenerator 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module BaudRateGenerator(
    input clock,
    output reg tick
    );
	 
localparam  CUENTA = 1'b0,
				TICK = 1'b1;

reg current_state, next_state;
reg [8:0] contador;

//Registro de estado (Memoria)
always @(posedge clock)
	begin
		current_state <= next_state;
	end

// Logica de salida
always @*
	begin
		case (current_state)
			CUENTA:
				begin
					tick = 1'b0;
				end
			TICK:
				begin
					tick = 1'b1;
				end
		endcase
	end

// Logica de cambio de estado
always @*
	begin
		case(current_state)
			CUENTA:
				begin
					if(contador < 326)
					begin
						next_state = CUENTA;
						contador = contador + 1;
					end
					else
					begin
						next_state = TICK;
						//contador = contador + 1;
					end	
				end
			TICK:
				begin
					next_state = CUENTA;
					contador = 0;
				end
		endcase
	end

endmodule
